The present invention relates to the field of integrated circuit and more specifically to trip-point adjustment and delay circuits.
There are many types of integrated circuit including microprocessors, ASICs, memories, gate arrays, and programmable logic. On an integrated circuit, various circuitry is used to implement different functions. For example, for a digital integrated circuit, logic gates are the basic building blocks. Despite the overwhelming success of integrated circuits in the marketplace, there is a constant demand for integrated circuits that have better performance or have greater functionality. One of the ways to meet the demand for integrated circuits with greater performance is to improve the circuitry of the integrated circuit.
A standard CMOS logic gate has a gate trip point that defines the voltage at the gate input at which the output transitions. For a CMOS gate, this trip point is usually near the middle of the voltage range (i.e., VCC/2). By adjusting the ratio of the PMOS pull-up network W/L versus the NMOS pull-down network W/L in the CMOS gate, this trip point can be adjusted to be higher or lower than VCC/2. For a standard CMOS inverter, the gate trip point as adjusted in the above manner is the same for both rising and falling inputs. In some applications, it is desirable to have an inverter or logic gate with a different trip point for a rising-edge input from the trip point for a falling-edge input.
Another type of circuit that is useful in an integrated circuit is a delay circuit. Delay circuits are used in various places in an integrated circuit and for various purposes. Delay circuits can be used in conjunction with the clocking tree to ensure logic signals do not arrive too early at sequential logic, latches, and flip-flops, relative to the latching clock (i.e., prevent hold time violations). Delay circuits can be used in delay-locked loops and phase-locked loops. It is important to have circuits where the delay can be tuned to have the precise delay desired. Also, the delay circuit should have a delay that is relatively constant given variations in the process, temperature, and supply voltage.
Therefore, there is a need for trip point adjustment circuit and delay chain circuit techniques.
An aspect of the invention is a circuit technique that provides for different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. This circuit may be useful in, for example, delay chain circuits and any logic where it is desirable to control independently the rising and falling delays. Another aspect of the invention is to provide different circuit topologies for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay (e.g., to meet a minimum timing specification), or to track another circuit delay (e.g., hold time delays that track the clock network path delay).
In an embodiment, the invention is a logic circuit including a logic gate connected between a first input and an output of the logic circuit. A first group of transistors is connected in series between a first supply and the output, where a first transistor of the first plurality is connected to the first input and a second transistor of the first plurality is connected to a second input. A second group of transistors connected in series between a second supply and the output, where a third transistor of the second plurality is connected to the first input and a fourth transistor of the second plurality is connected to the second input.
In another embodiment, the invention is an integrated circuit including a first logic gate, a second logic gate, and first, second, third, fourth, fifth, sixth, seventh, and eighth resistances. A first conductor connects the first logic gate to the first resistance, a second conductor connects the first resistance to the second resistance, a third conductor connects the second resistance to the third resistance, a fourth conductor connects the third resistance to the fourth resistance, a fifth conductor connects the fourth resistance to the fifth resistance, a sixth conductor connects the fifth resistance to the sixth resistance, a seventh conductor connects the sixth resistance to the seventh resistance, and an eighth conductor connects the seventh resistance to the eighth resistance. A ninth conductor connects the second logic gate to the first conductor through a first metal option, second conductor through a second metal option, third conductor through a third metal option, fourth conductor through a fourth metal option, fifth conductor through a fifth metal option, sixth conductor through a sixth metal option, seventh conductor through a seventh metal option, and eighth conductor through an eighth metal option.
In yet another embodiment, the invention is an integrated circuit including first, second, third, and fourth logic gates. A first resistance is between the second logic gate and a first conductor, a second resistance is between a second conductor and the third logic gate, a third resistance is between the third logic gate and a third conductor, and a fourth resistance is between a fourth conductor and the fourth logic gate. A first metal option is between first and second conductors, and a second metal option between third and fourth conductors.